The FEIP is a fixed-configuration interface processor that provides up to two, IEEE 802.3u, 100BASE-T Fast Ethernet (FE) interfaces. The FEIP uses a Reduced Instructions Set Computing (RISC), MIPS 4600 processor for high performance, and has an internal operating frequency of 100 megahertz (MHz) and a 50-MHz system bus interface. The FEIP has 8 megabytes (MB) of dynamic random access memory (DRAM). The FEIP microcode image is contained in the microcode ROM (U37).